ATE-FIT5

AMfoRS' TIMA Emulation-based Fault Injection plaTform on Virtex-5


Significant effort has been targeted by team members since more than fifteen years on developing efficient techniques to analyze, at design time and early in the design flow, the functional consequences of soft errors in synchronous digital circuits or systems (including embedded software). This has led to several approaches for early fault injections, based either on simulation or emulation and using or not an intrusive instrumentation technique. Most of the proposed techniques start from synthesizable RTL descriptions, because such descriptions are already close to the final hardware in terms of cycle accuracy and in terms of memory cells identification thus lead to more accurate results than higher-level descriptions while allowing shorter experimental times and earlier results than gate-level netlist-based analyses.

The current state-of-the-art platform is based on a non-intrusive approach (no instrumentation of the design under evaluation) and on emulation on FPGAs to improve performances (the improvement with respect to RTL simulation was shown to be several orders of magnitude, allowing a much more extensive fault injection campaign in a given time frame - the improvement with respect to gate-level simulation is several orders of magnitude higher). The system under evaluation must be available as a synthesizable description (usually at RT-Level) potentially including compiled embedded software.

This is completed by the possibility to perform statistical fault injection, with a defined margin of error on the classification results (e.g., percentage of silent errors or detected errors) for a given confidence level.

Errors are injected in flip-flops for functional effect analysis. Injecting errors may be done using the most generic model called "bit-flip" (inversion of the current value), but can also easily be done according to other models (bit-set, bit-reset, or even stuck-at, transient or permanent). The multiplicity of errors at each injection cycle can be specified. Analyses may lead to several goals, see more details in the page Hardware/Software dependability analysis from RT-Level descriptions.

The most advanced version of the platform has been called ATE-FIT5 and is available for
free download . This platform is based on Virtex 5 boards, so that dependability evaluations can be performed on critical IPs at low cost. Part of the development effort has been supported by ANR in the framework of the project "LIESSE" (ANR-2012-INSE-0008). Specific error models, such as the model developped in the project LIESSE to take into account the locality of laser attacks, can also be used (and have been used during the project) on the ATE-FIT5 platform. Details on the laser local model can be found in:

A. Papadimitriou*, D. Hély*, V. Beroulle*, P. Maistri, R. Leveugle
"A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks"
Design, Automation and Test in Europe Conference (DATE), March 24-28, 2014
* LCIS, France

Contact

Régis Leveugle
TIMA Laboratory
46 avenue Félix Viallet
38031 Grenoble Cedex
FRANCE
E-mail: Regis.Leveugle[at]imag.fr


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