Salvador Mir
Laboratoire TIMA
46, Av. Félix Viallet
38031 Grenoble, France
e-mail: salvador.mir [AT]
phone: +33 (0) 4 76 57 48 95



Academic Background

I received an Industrial Engineering (Electrical, 1987) degree from the Polytechnic University of Catalonia, Barcelona, Spain, M.Sc. (1989) and Ph.D. (1993) degrees in Computer Science from the University of Manchester, UK, and the “Habilitation à Diriger des Recherches” from Institut Polytechnic de Grenoble, France (2005). I am a Research Director of the French National Center for Scientific Research (CNRS), and Director of TIMA Laboratory in Grenoble since January 2015. I have lead the RMS (Reliable Mixed-signal Systems) Group since January 2002 until December 2014.


Current research lines

These are the research lines I have been involved with in the last 10 years.

Research lines

Research topics

Computer-Aided test and diagnosis for mixed-signal/RF CMOS circuits

Test metrics estimation
Machine-learning based test
Parameter identification based test and control
Machine-learning based fault diagnosis
Mixed-signal CAT platform

Design-for-test of mixed-signal/RF  CMOS circuits

Sigma-Delta ADC BIST
Pipeline ADC test
CMOS imager BIST

Design and test of MEMS

Pseudorandom MEMS BIST
MEMS Design

Curriculum Vitae

For a reasonably up-to-date version, click here.


For a complete list of publications (reasonably up-to-date), click here. These are some of the most often cited journal publications:

    B. Charlot, S. Mir, F. Parrain and B. Courtois. Generation of electrically induced stimuli for MEMS self-test. Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, 17(6):459-470, December 2001.

    S. Mir, B. Charlot and B. Courtois. Extending fault-based testing to Microelectromechanical Systems. Journal of Electronic Testing : Theory and Applications, Kluwer Academic Publishers, 16(3):279-288, June 2000.

    M. Lubaszewski, S. Mir, V. Kolarik, C. Nielsen and B. Courtois. Design of self-checking fully differential circuits and boards. IEEE Transactions on VLSI Systems, 8(2):113-128, April 2000.

    A. Bounceur, S. Mir, E. Simeu and L. Rolíndez. Estimation of test metrics for the optimisation of analogue circuit testing. Journal of Electronic Testing: Theory and Applications, Springer Science+Business Media, 23(6), 2007, pp. 471-484.

    H. Stratigopoulos, S. Mir and A. Bounceur. Evaluation of analog/RF test measurements at the design stage. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 4, April 2009, pp. 582-590.